Design AXI Master IP using Vivado HLS tool
IPs based on advanced algorithms is the need for applications like wireless, medical, defense and consumer. In such scenarios, Vivado® High-Level Synthesis (HLS) accelerates creation of IPs by enabling C, C++ or System C based specifications to be directly targeted to Xilinx All Programmable devices without the need of manually developing RTL code.
This paper concludes with:
- Usage of Vivado® HLS in creating AXI Master IP and its advantages.
- Steps used in Vivado® HLS to implement AXI master.
- The AXI Master block is useful in transferring data from FPGA fabric to ARM-based processor system and contribute significantly in improving the performance of the HEVC Decoder on Zynq.
This document contains details regarding product information, standards, and technical specifications.