The Irreplaceable Utility of FPGA-based HEVC for Video Streaming

Date: November 26, 2018

Author: Vikas Srivastava

High Efficiency Video Coding (HEVC), the video coding standard in video compression, was developed to provide high quality video coding using significantly lower bandwidth than its predecessor H.264. HEVC made it possible to compress the video at a remarkably lower bitrate compared to the previous video coding standard, Advanced Video Coding (AVC), with the same video quality.

Superior Compression, Higher Quality

Development of HEVC started immediately after the preceding video coding standard (AVC) was pushed to the market in 2003.

While AVC delivered significantly better compression ratios compared to MPEG2 and MPEG4 video coding standards, it could not keep up with the requirements for 4K content. On the other hand, HEVC standard employed complex algorithms - for motion estimation, frame prediction and the partitioning of coding block units – which resulted in doubled compression ratios of coded content compared to its predecessor AVC.


H.264/H.265 Visual Comparison

As we are aware, the latest television technology (4K) contains four times the number of pixels as 1080p (full HD) and without HEVC, broadcasters wanting to transmit programs in 4K quality face the challenge of the compulsive presence of high-quality broadband reception to make 4K broadcasts a reality.

A benefit of HEVC is that it makes broadcasting 4K more feasible - reducing both the cost and time it takes to deliver high quality programming. Its algorithm uses efficient coding by encoding video at a lower bit rate and transmits the smallest amount of information necessary for a specified level of video quality thereby maintaining a high image quality level. This saves bandwidth cost and also enables higher quality television delivery over the internet and other media channels.

The Efficiency v/s Compute Power Trade-Off

HEVC/H.265 comes with the trade-off requiring almost 10x more computing power. Higher compression efficiency in HEVC came with increased computational complexity, making real time encoding/decoding of high-resolution videos a challenging task.

As designs became more and more complex, it was perceived that traditional hardware (HW) description languages (HDLs), such as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) or Verilog, can’t be used to present the designs without increasing effort as well as risks. This challenge was although addressed by software but simultaneously it was concluded that hardware solutions are more suited. However, with the help of certain modifications over time and considering factors such as latency, performance, power consumption and flexibility of implementation, the target application gets to decide whether a hardware specific solution or a software will suit the requirement.

The Strong Case of HEVC on FPGA

The popularization of a 4K/8K video being dependent on the availability of real-time High Efficiency Video Coding (HEVC) decoders made hardware implementations more appealing due to their superior performance and low power consumption. FPGA-based HEVC decoders offer real-time performance for UHD videos with ultra-low latency & optimized resource utilization. With the advent of today’s SoC based FPGAs, FPGAs can also be used as hardware accelerators for implementing compute intensive modules like Motion estimation & compensation, Prediction etc. Major FPGA vendors such as Altera and Xilinx currently offer very powerful SoC platforms for development, prototyping, and production, as they provide both flexibility and performance. As the complexity of video codec algorithm increases over time, these types of FPGA-based decoders will be ideal to address such complexity.

An FPGA based HEVC Decoder Delivers on the following Fronts

Performance: Since FPGAs are (or, can be configured as) parallel processing devices, an entire algorithm gets executed in far fewer clock ticks than it takes a sequential processor. As one of the costs to the increased logic complexity - typically a lower limit at which the device can be clocked - gets reduced, it elevates the performance of an FPGA based decoder and makes it possible to compress the video at a remarkably lower bitrate compared to AVC, that too at the same video quality.

Ease of Modification: Since the Hardware structure in the FPGA is not fixed, it makes it possible to customize the decoder according to user's preferences. Despite logic cells being fixed in FPGA, the intended functions they are about to perform and the interconnections between them are determined by the user. One can have the processes done according to the written HDL code in a parallel fashion. Ability of parallel processing is one of the most important features that separates FPGA based decoder from its other variants and make it superior in many areas.

Low Power Consumption: Power savings are a further advantage gained by FPGA based HEVC decoders as compared to its competitors. Optimized FPGAs help the HEVC decoders in achieving massive performance gains with smaller power requirements. They also come with Low-power modes which are very useful and can provide a lot of power saving in application where system does not need to be in active state 100% of the time.

Video Processing: No other solution is as much suited to process a high-resolution video data as an FPGA based HEVC decoder. Because video processing requires processing large data at high speeds, such applications are very suitable for FPGA’s structure which are designed to perform parallel processing.


Leading Researchers, analysts and tech observers are of the opinion that “HEVC usage would dominate in distribution to OTT and connected TV devices, with a significant pickup in HEVC distributed via HLS to Apple desktops, mobile devices, and the AppleTV 4K”. And to answer the parallel onslaught of content on various streaming platforms while maintaining quality, FPGA based HEVC decoders – with its string of benefits - will be the best bet.


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