HEVC Decoder

Video Quality has evolved dramatically over the last decade. Now we have sharper pictures with better colours and that evolution is in full swing with 4K ultra HD. 4K demands new technology to enable video that can still be broadcast at the desired quality. One of those technologies is HEVC or H.265. It is an essential technology for systems which have forayed into next-gen multimedia solutions.

PathPartner's HEVC 4K Decoder on FPGA is a cutting edge video decompression engine that offers real-time performance for 4K videos with ultra-low latency & optimized resource utilization. Although targeted primarily at FPGAs, it is well suited for intel i5 and ARM multi-core processor platforms too.

HEVC FPGA Decoder - Features

Compliance

It is fully compliant to the ISO/ IEC 23008-2 and ITU-T H.265 standards.

Implementation

Available as Full Hardware (FPGA only) as well as Hybrid Hardware/Software (FPGA + ARM)

Performance

Scalable up to 4k60 fps decoding, it Supports Monochrome, 4:2:0, 4:2:2 chroma formats and bit depth of 8 bits, 10 bits and 12 bits.

Optimization

It’s a Universal HEVC Main profile Decoder with Multi Platform Support. The Configurable nature offers unmatched error concealment & resilience.

Flexibility

The decoder is scalable across low, mid and high-range FPGA Platforms. Currently powered by Xilinx KU040 and KU060 devices, it is also effortlessly portable on Altera platform.

Applications

With its multi-application relevance, these decoders are customizable for Broadcast, Defence, Aviation, Drones, Automotive and Gaming segments.

Video Format

Supports all the resolutions Up-to 4k at a maximum frame rate of 60. Supports high bit rate and resolutions up to 8K.

Cloud Presence

Available on Amazon Web Services (AWS) as FFMPEG plugin. Anyone using FFMPEG in AWS workflow can invoke HEVC 4K decoder by using a simple prefix -c:v pphevcdec. Library available as an AMI (Amazon Machine Image).

Interfaces

The IO interface comprises of an input FIFO and an accessible outputframe buffer to encode, decode and display data. Data display can also happen through a separate AXI4 stream. For configuration, AXI4 Lite acts as a bridge between decoder and host.

Other Platforms

HEVC Decoder on Intel i5

With a Performance of 4K @ 60fps at Level 5.1 on Intel Haswell, it supports Main & Main10 at level 5 and Main 12, Main 4:2:2 10, Main 4:2:2 12 Range extension profiles that allows for a bit depth of 8-bits to 12-bits per sample. With a portable multi-threaded design and an advanced AVX2 Acceleration vector extension, the decoder is highly scalable and supports resolutions up to 8K.

HEVC Decoder on FPGA

  • Targeted on Xilinx Kintex Ultrascale or Altera Arria-10
  • Up to 1080p @120 fps and 4KP60 resolution supported
  • Multichannel / Multistream decoding capable
  • Decoder supports Main profiles and up to Level 5.1
  • Supports 4:2:2 & 4:2:0 chroma format
  • Support bit-depth of 8/10/12-bit
  • Support for high bitrate
  • Supports I frame or I & P frame or IPB frames decoding
  • Optimized FPGA & Memory Utilization
  • Unmatched Error Concealment / Resiliency
  • Ultra Low Latency
  • Full HW (FPGA only) or Hybrid HW/SW (FPGA + ARM) implementation
  • Flexible SoC System integration with Standard APIs
  • Fully Tested on hardware platform with industry compliance streams

HEVC Decoder on ARM

With a Performance of 4K @ 24fps, Main profile is housed on ARM 2.3 GHz. It supports Main & Main10 at level 5 and Main 12, Main 4:2:2 10, Main 4:2:2 12 Range extension profiles that allows for a bit depth of 8-bits to 12-bits per sample. With a portable multi-threaded design and an advanced NEON Acceleration vector extension, the decoder is highly scalable and supports resolutions up to 8K.

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