I2S (Inter-IC Sound) is a serial bus interface standard used to connect various audio devices together. I2S interface handles audio data separately from clock signals. Therefore, jitter is less compared to other communication systems.
I2S is widely used in a variety of applications such as compact disk (CD) players, digital sound processors, digital TV (DTV) sound.
IC manufacturers have been using dedicated audio interfaces in ICs for many years, instead of one standard protocol. But, it becomes very difficult to interface the devices to each other without any common standard. Introduction of I2S filled this gap and provided us with easy connectivity for digital audio devices.
There are many standards for transmitting digital audio data. For example, I2S, TDM, S/PDIF etc. I2S provides an easy way of sending/receiving PCM audio and it enables us to interface I2S based audio DAC/ADC.
Inter-IC Sound (pronounced as “I-squared-S” or “I-two-S”) is the most common digital audio format used for audio data transfer between ICs. The I2S standard was introduced by Philips Semiconductors (now NXP) in 1986 and was revised in 1996. The interface was first popularly used in CD player designs and presently it is an integral part of many applications where digital audio data is being transferred from one IC to another. Most audio DACs, ADCs, DSPs & sample rate converters, and some microcontrollers use I2S interfaces.
We, at PathPartner have developed I2S transmitter and receiver targeted for Xilinx FPGA platform. The design is compliant with 'Philips Inter-IC Sound Bus Specification'. The functionality of I2S Transmitter and Receiver is independent of each other. It can be utilized as a single Tx/Rx or both active together. The input word length is configurable. It can handle 16-bit, 32-bit and 64-bit audio data input.
In this blog, we will discuss about standard I2S interface and an efficient approach to design I2S transmitter and receiver. The design is fully synthesizable and targeted towards optimal FPGA implementation with minimum resource utilization.
An I2S bus uses three signal lines for data transfer: a bit clock, word select clock and a data line.
- Continuous serial clock (SCK) or Bit clock (BCLK): It provides single bit clock
- Word select (WS) or Left Right clock (LRCLK): It indicates the channel on which data is being transmitted
- When WS = 0 or low, Left Channel data is transferred
- When WS = 1 or high, Right Channel data is transferred
- Serial data Input (SD IN): It follows 2-channel time-division multiplexed format
Either transmitter or receiver can be a master depending upon system architecture. The master generates BCLK and LRCLK. In case of multiple transmitters and receivers, there is one master controller which controls the data flow.
Our design implements a single transmitter-receiver pair. I2S transfers audio data to and from ADC which acts as a master controller and generates the clock. I2S Tx/Rx are configured to operate in slave mode. The design is implemented on FPGA, where the stereo input is provided through 'Line In' port and output is tested through 'headphone out' port.
- Supports 16-bit, 24-bit and 32-bit sampling data width
- Multichannel Support (can transmit/receive audio data on 8 or 16 audio channels)
- Supports 1.0 I2S specifications
- Transmit and Receive operation with Left and Right channel support
- Supports programmable padding
- Synchronous FIFO with configurable width support for received data
- Loop back mode for testing purpose
- Variable sampling rate support, used in slave mode
The design is implemented in such a way that it can operate in one of the following modes:
- Transmitter only
- Receiver only
- Transmitter and Receiver both active simultaneously
The interface is synchronized to 100 MHz system clock frequency. However, it is flexible. The clock need not be a multiple of the clock input to audio interface.
Below figure shows the I2S block level design. Here, 'n' indicates input data width which can be 16, 24 or 32 and 'm' indicates number of channels (8 or 16).
I2S receives bit clock and serial data input on 'bclk' and 'sd' input lines respectively from audio chip. It receives word select input on 'lrclk' pin. Audio chip is clocked at a frequency of 1024 times the base sampling rate. If we consider a sampling rate of around 48 kHz, the frequency turns out to be 50 MHz. This is the clock input to the master controller.
LR clock must be held constant for 64 clock cycles at least; to latch the data properly. Serial clock is calculated as ‘(sampling frequency*Number of bits per channel*Number of channels)’. The calculation fetches the value of bit clock frequency to be around 3 MHz.
PCM data from all the channels is fed to a shift register serially by I2S receiver. FIFO stores the parallel data received from I2S receiver. It operates at the same system clock frequency and it can store as many as 128 samples, each of either 32 or 48 or 64 bits; depending upon the input width. It loops back the data to I2S transmitter. The parallel data is shifted serially and serial output is transmitted on all the channels.
The figure below depicts data flow:
The serial input data is captured on each rising edge of BCLK and shifted left bit-by-bit. We have implemented shifted version of BCLK instead of its raw version to handle metastability issues. When LRCLK transition occurs, the parallel data is provided as input to FIFO. It is a synchronous FIFO with 'empty' and 'full' flags to indicate the status of fifo. Output valid pulse is generated to indicate the valid output. The same signal is used as 'write enable' to the fifo. That means whenever valid data is available on output data bus, we will keep writing it to FIFO.
The data is read from FIFO on assertion of 'read enable'. It is looped back and given as left channel data and right channel data input to I2S. 'Zero padding' is done to adjust the data width as per input data format. For example, if the audio input is 8-bit per channel, 16 zeroes are padded per channel so that the data bus width of 32 per channel is maintained. The data is shifted left. The transmitter always sends the MSB of the next word, one clock period after the LRCLK changes. The LRCLK signal is latched on the trailing edge of the clock signal. Serial data sent by the Transmitter is also synced with the trailing edge of the SCLK.
The MSB of parallel shift register is sampled as serial output on each falling edge of bclk.
- Configurable options
- Independent transmitter and receiver mode
- Multiple channel input and output
The audio I2S interface IP is tested on FPGA with loopback for audio PCM data ensuring minimum resource utilization.